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authorJoerg Roedel <jroedel@suse.de>2018-08-10 11:24:32 +0200
committerJoerg Roedel <jroedel@suse.de>2018-08-10 11:24:53 +0200
commitce8dfdccb4fecfa619af41f13dbfe3098e592ecd (patch)
tree3d710bea8b9de184914bdd2ba201a2c4bcdd9bb8
parent84fe3585eace4f27eae4ebd4dcde19ecd8e87acc (diff)
x86/CPU/AMD: Derive CPU topology from CPUID function 0xB when
-rw-r--r--arch/x86/kernel/cpu/amd.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 2638475d6c65..c84297fd8085 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -327,6 +327,7 @@ static void amd_get_topology(struct cpuinfo_x86 *c)
/* get information required for multi-node processors */
if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
+ int err;
u32 eax, ebx, ecx, edx;
cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
@@ -345,6 +346,14 @@ static void amd_get_topology(struct cpuinfo_x86 *c)
}
/*
+ * In case leaf B is available, use it to derive
+ * topology information.
+ */
+ err = detect_extended_topology(c);
+ if (!err)
+ c->x86_coreid_bits = get_count_order(c->x86_max_cores);
+
+ /*
* We may have multiple LLCs if L3 caches exist, so check if we
* have an L3 cache by looking at the L3 cache CPUID leaf.
*/
@@ -394,7 +403,6 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c)
c->phys_proc_id = c->initial_apicid >> bits;
/* use socket ID also for last level cache */
per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
- amd_get_topology(c);
#endif
}
@@ -857,6 +865,7 @@ static void init_amd(struct cpuinfo_x86 *c)
/* Multi core CPU? */
if (c->extended_cpuid_level >= 0x80000008) {
amd_detect_cmp(c);
+ amd_get_topology(c);
srat_detect_node(c);
}