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authorRoger Quadros <rogerq@ti.com>2018-12-05 19:27:44 +0200
committerTony Lindgren <tony@atomide.com>2018-12-07 08:25:02 -0800
commita763ecc15d0e37c3a15ff6825183061209832685 (patch)
treef79b6694174d2419106cce983b29133bbd15b9f5
parent91e43395820baad80248987608216c35da9df65b (diff)
ARM: dts: omap5: Fix dual-role mode on Super-Speed port
OMAP5's Super-Speed USB port has a software mailbox register that needs to be fed with VBUS and ID events from an external VBUS/ID comparator. Without this, Host role will not work correctly. Fixes: 656c1a65ab55 ("ARM: dts: omap5: enable OTG role for DWC3 controller") Reported-by: H. Nikolaus Schaller <hns@goldelico.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r--arch/arm/boot/dts/omap5-board-common.dtsi1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi
index bf7ca00f4c21..bc853ebeda22 100644
--- a/arch/arm/boot/dts/omap5-board-common.dtsi
+++ b/arch/arm/boot/dts/omap5-board-common.dtsi
@@ -701,6 +701,7 @@
};
&dwc3 {
+ extcon = <&extcon_usb3>;
dr_mode = "otg";
};