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authorThomas Gleixner <tglx@linutronix.de>2008-09-06 03:06:08 +0200
committerGreg Kroah-Hartman <gregkh@suse.de>2008-10-08 19:44:43 -0700
commit22e4330618d27748cc69b62d3c96223bcefe6c6c (patch)
tree8b2c2f4e0f15b8fb75a284093d2ccfb3db4e4b1e
parent59ff733c6b6ef547bb09a9902020750dfbb2200f (diff)
x86: HPET: read back compare register before reading counter
commit 72d43d9bc9210d24d09202eaf219eac09e17b339 upstream After fixing the u32 thinko I sill had occasional hickups on ATI chipsets with small deltas. There seems to be a delay between writing the compare register and the transffer to the internal register which triggers the interrupt. Reading back the value makes sure, that it hit the internal match register befor we compare against the counter value. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
-rw-r--r--arch/x86/kernel/hpet.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index 791c369dd813..bec6496a3643 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -290,6 +290,13 @@ static int hpet_legacy_next_event(unsigned long delta,
cnt += (u32) delta;
hpet_writel(cnt, HPET_T0_CMP);
+ /*
+ * We need to read back the CMP register to make sure that
+ * what we wrote hit the chip before we compare it to the
+ * counter.
+ */
+ WARN_ON((u32)hpet_readl(HPET_T0_CMP) != cnt);
+
return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
}