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| author | Michal Kubecek <mkubecek@suse.cz> | 2019-10-16 15:39:51 +0200 |
|---|---|---|
| committer | Michal Kubecek <mkubecek@suse.cz> | 2019-10-16 15:39:51 +0200 |
| commit | 237b4cc83eb90cb10c6a1bf73597b5ec619d9e5d (patch) | |
| tree | a583ba8aed68886f3fc007aa93420bb6b028cce9 | |
| parent | ffdd09497548db5314d6c615399f3c7533844f17 (diff) | |
| parent | afd94706525ae437bf9d6a0d80ff6b5f32239fe1 (diff) | |
Merge branch 'users/ykaukab/SLE15-SP2/for-next' into SLE15-SP2rpm-5.3.6-1--SLE-15-SP2-Full-Alpha5rpm-5.3.6-1
Pull ARM patch cleanup and git-fixes from Mian Yousaf Kaukab.
suse-commit: adff98892a872dc45263067b728af2d0598fba0f
| -rw-r--r-- | drivers/ata/libahci.c | 18 | ||||
| -rw-r--r-- | drivers/pci/quirks.c | 26 | ||||
| -rw-r--r-- | drivers/pinctrl/pinctrl-rockchip.c | 1 |
3 files changed, 45 insertions, 0 deletions
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c index e4c45d3cca79..b15bd71aaf5c 100644 --- a/drivers/ata/libahci.c +++ b/drivers/ata/libahci.c @@ -667,6 +667,24 @@ int ahci_stop_engine(struct ata_port *ap) tmp &= ~PORT_CMD_START; writel(tmp, port_mmio + PORT_CMD); +#ifdef CONFIG_ARM64 + /* Rev Ax of Cavium CN99XX needs a hack for port stop */ + if (dev_is_pci(ap->host->dev) && + to_pci_dev(ap->host->dev)->vendor == 0x14e4 && + to_pci_dev(ap->host->dev)->device == 0x9027 && + midr_is_cpu_model_range(read_cpuid_id(), + MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN), + MIDR_CPU_VAR_REV(0, 0), + MIDR_CPU_VAR_REV(0, MIDR_REVISION_MASK))) { + tmp = readl(hpriv->mmio + 0x8000); + udelay(100); + writel(tmp | (1 << 26), hpriv->mmio + 0x8000); + udelay(100); + writel(tmp & ~(1 << 26), hpriv->mmio + 0x8000); + dev_warn(ap->host->dev, "CN99XX SATA reset workaround applied\n"); + } +#endif + /* wait for engine to stop. This could be as long as 500 msec */ tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index b9d0fcda2aec..c5fc1f69ee5a 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4028,6 +4028,32 @@ static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); +#if IS_ENABLED(CONFIG_ARM64) +/* + * PCI BAR 5 is not setup correctly for the on-board AHCI controller + * on Broadcom's Vulcan processor. Added a quirk to fix BAR 5 by + * using BAR 4's resources which are populated correctly and NOT + * actually used by the AHCI controller. + */ +static void quirk_fix_vulcan_ahci_bars(struct pci_dev *dev) +{ + struct resource *r = &dev->resource[4]; + + if (!(r->flags & IORESOURCE_MEM) || (r->start == 0)) + return; + + /* Set BAR5 resource to BAR4 */ + dev->resource[5] = *r; + + /* Update BAR5 in pci config space */ + pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, r->start); + + /* Clear BAR4's resource */ + memset(r, 0, sizeof(*r)); +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9027, quirk_fix_vulcan_ahci_bars); +#endif + /* * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are * associated not at the root bus, but at a bridge below. This quirk avoids diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 62a622159006..dc0bbf198cbc 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -2792,6 +2792,7 @@ static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, * still return -ENOTSUPP as before, to make sure the caller * of gpiod_set_debounce won't change its behaviour. */ + return -ENOTSUPP; default: return -ENOTSUPP; } |