Home Home > GIT Browse
summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorMichael Chan <mchan@broadcom.com>2005-02-10 20:42:59 -0800
committerDavid S. Miller <davem@nuts.davemloft.net>2005-02-10 20:42:59 -0800
commit6d04c7b7bc8ecb364849c50d4ff417918da71f8b (patch)
tree9f5b5c26e6a5b5770f90c861d0823c62b7357766
parentd79b8eeea88bfb6a98b577bcb1869e0179ebfb41 (diff)
[TG3]: capacitive coupling detection fix
This patch fixes the problem reported in: http://marc.theaimsgroup.com/?l=linux-kernel&m=110798711911645&w=2 The 5700 link problem was caused by reading uninitialized values in sram and causing capacitive coupling mode to be enabled by mistake. This patch fixes the problem by properly validating the sram contents. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/tg3.c10
-rw-r--r--drivers/net/tg3.h3
2 files changed, 11 insertions, 2 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 789b9086b717..60371454433b 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -7503,12 +7503,18 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
if (val == NIC_SRAM_DATA_SIG_MAGIC) {
u32 nic_cfg, led_cfg;
- u32 nic_phy_id, cfg2;
+ u32 nic_phy_id, ver, cfg2 = 0;
tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
tp->nic_sram_data_cfg = nic_cfg;
- tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
+ tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
+ ver >>= NIC_SRAM_DATA_VER_SHIFT;
+ if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
+ (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
+ (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
+ (ver > 0) && (ver < 0x100))
+ tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
eeprom_signature_found = 1;
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 02b75de37af8..629f1897e322 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1452,6 +1452,9 @@
#define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000
#define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000
+#define NIC_SRAM_DATA_VER 0x00000b5c
+#define NIC_SRAM_DATA_VER_SHIFT 16
+
#define NIC_SRAM_DATA_PHY_ID 0x00000b74
#define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000
#define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff