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authorAnton Blanchard <anton@samba.org>2003-10-17 09:16:49 +1000
committerAnton Blanchard <anton@samba.org>2003-10-17 09:16:49 +1000
commit600223fe334f62ad2eb37b979ac9ea0e89e99899 (patch)
treebd5c18809506fd6c9e7cf0c8422be2798553a423
parentcb57e089f961eb8abe3531cf29c0bda65b2ffb52 (diff)
ppc64: Fix for sym2 problem (first place that checked pci_set_mwi return code)
-rw-r--r--include/asm-ppc64/pci.h13
1 files changed, 8 insertions, 5 deletions
diff --git a/include/asm-ppc64/pci.h b/include/asm-ppc64/pci.h
index 8862dc52c483..da09c77b8123 100644
--- a/include/asm-ppc64/pci.h
+++ b/include/asm-ppc64/pci.h
@@ -34,12 +34,15 @@ struct pci_dev;
#define HAVE_ARCH_PCI_MWI 1
static inline int pcibios_prep_mwi(struct pci_dev *dev)
{
- /*
- * pSeries firmware sets cacheline size and hardware treats
- * MWI the same as memory write, so we dont change cacheline size
- * or the MWI bit.
+ /*
+ * We would like to avoid touching the cacheline size or MWI bit
+ * but we cant do that with the current pcibios_prep_mwi
+ * interface. pSeries firmware sets the cacheline size (which is not
+ * the cpu cacheline size in all cases) and hardware treats MWI
+ * the same as memory write. So we dont touch the cacheline size
+ * here and allow the generic code to set the MWI bit.
*/
- return 1;
+ return 0;
}
extern unsigned int pcibios_assign_all_busses(void);