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authorBorislav Petkov <bp@suse.de>2019-05-19 00:22:27 +0200
committerBorislav Petkov <bp@suse.de>2019-05-19 00:22:32 +0200
commit35bcc1cf7761c23c8b316b3ce5808e9a876be49e (patch)
tree80c938e6235dc37c2adbf2486f201df897b7daf9
parent1d5885087bac734101df003160748d5e1d16525f (diff)
x86/mce: Don't disable MCA banks when offlining a CPU on AMD
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 161edcb766c5..e2d22c4ae88d 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1940,12 +1940,13 @@ static void mce_disable_error_reporting(void)
static void vendor_disable_error_reporting(void)
{
/*
- * Don't clear on Intel CPUs. Some of these MSRs are socket-wide.
+ * Don't clear on Intel or AMD CPUs. Some of these MSRs are socket-wide.
* Disabling them for just a single offlined CPU is bad, since it will
* inhibit reporting for all shared resources on the socket like the
* last level cache (LLC), the integrated memory controller (iMC), etc.
*/
- if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
+ boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
return;
mce_disable_error_reporting();