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authorDave Airlie <airlied@redhat.com>2014-11-28 13:56:31 +1000
committerDave Airlie <airlied@redhat.com>2014-11-28 13:56:31 +1000
commit21124e5c52ecf87c3fdcb03855ec852563ce93cf (patch)
treedb610467ee8b6552d2ad784ca1c33b3d8168d753
parent8e4890fbfb8af675a3800cbbc3463825c372cf78 (diff)
parentafa4e53a7bcd4328d88e25c7a63746b65dc6bbe2 (diff)
Merge tag 'drm-intel-fixes-2014-11-27' of git://anongit.freedesktop.org/drm-intel into drm-fixes
Two regression fixes from Ville. * tag 'drm-intel-fixes-2014-11-27' of git://anongit.freedesktop.org/drm-intel: drm/i915: Cancel vdd off work before suspend drm/i915: Ignore SURFLIVE and flip counter when the GPU gets reset
-rw-r--r--drivers/gpu/drm/i915/intel_display.c4
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c1
2 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f0a1a56406eb..8bcdb981d540 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9408,6 +9408,10 @@ static bool page_flip_finished(struct intel_crtc *crtc)
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ if (i915_reset_in_progress(&dev_priv->gpu_error) ||
+ crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
+ return true;
+
/*
* The relevant registers doen't exist on pre-ctg.
* As the flip done interrupt doesn't trigger for mmio
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5ad45bfff3fe..4bcd91757321 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4450,6 +4450,7 @@ static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
* vdd might still be enabled do to the delayed vdd off.
* Make sure vdd is actually turned off here.
*/
+ cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
pps_lock(intel_dp);
edp_panel_vdd_off_sync(intel_dp);
pps_unlock(intel_dp);