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authorTakashi Iwai <tiwai@suse.de>2019-05-24 20:37:03 +0200
committerTakashi Iwai <tiwai@suse.de>2019-05-24 20:37:03 +0200
commit8d868c9924d27f9a1cc01987ebd3aeb9eb19f761 (patch)
treeed002ac86f8c3f63ea23d8606836035d4ab39bfd
parentee3c6a4fcede241814b95e521ce0638f5ee8acf8 (diff)
drm/i915/gvt: do not let TRTTE and 0x4dfc write passthroughSLE15
to hardware (bsc#1051510). suse-commit: 7358223589a24e13b0898003b38d3dc29f13396c
-rw-r--r--drivers/gpu/drm/i915/gvt/handlers.c15
1 files changed, 0 insertions, 15 deletions
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 9be639aa3b55..5afbe2f571d9 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1282,7 +1282,6 @@ static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
- struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
u32 trtte = *(u32 *)p_data;
if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
@@ -1291,11 +1290,6 @@ static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
return -EINVAL;
}
write_vreg(vgpu, offset, p_data, bytes);
- /* TRTTE is not per-context */
-
- mmio_hw_access_pre(dev_priv);
- I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset));
- mmio_hw_access_post(dev_priv);
return 0;
}
@@ -1303,15 +1297,6 @@ static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
- struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
- u32 val = *(u32 *)p_data;
-
- if (val & 1) {
- /* unblock hw logic */
- mmio_hw_access_pre(dev_priv);
- I915_WRITE(_MMIO(offset), val);
- mmio_hw_access_post(dev_priv);
- }
write_vreg(vgpu, offset, p_data, bytes);
return 0;
}