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authorThomas Zimmermann <tzimmermann@suse.de>2019-05-14 09:15:19 +0200
committerThomas Zimmermann <tzimmermann@suse.de>2019-05-14 09:59:44 +0200
commitaea1b35962f3f2ebe383ff21888e5c6d7bc025db (patch)
tree931d2aedc88b64159587e0808caf521c625e9f80
parent61ca1eb22237dfa650bb8cacfcf0e538af5d709d (diff)
drm/i915/gvt: Fix incorrect mask of mmio 0x22028 in gen8/9 mmio list (bnc#1113722)
-rw-r--r--drivers/gpu/drm/i915/gvt/mmio_context.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index c563457de000..3d2d36df3603 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -79,7 +79,7 @@ static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
{BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
{BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
{BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
- {BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */
+ {BCS, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
{RCS, INVALID_MMIO_REG, 0, false } /* Terminated */
};
@@ -130,7 +130,7 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
{BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
{BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
{BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
- {BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */
+ {BCS, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
{VCS2, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */