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authorBorislav Petkov <bp@suse.de>2019-05-17 18:21:12 +0200
committerBorislav Petkov <bp@suse.de>2019-05-17 18:21:12 +0200
commit5dfccf98d8e3de00763b9d0b8bc4a8f97cb7b37d (patch)
tree41b32b177cbb4dddebacde9c95711254d4caeecc
parent79134f014967e6654ef8b2786b26f9da032998df (diff)
x86/cpu/mtrr: Support TOP_MEM2 and get MTRR number
-rw-r--r--patches.arch/x86-cpu-mtrr-support-top_mem2-and-get-mtrr-number.patch55
-rw-r--r--series.conf1
2 files changed, 56 insertions, 0 deletions
diff --git a/patches.arch/x86-cpu-mtrr-support-top_mem2-and-get-mtrr-number.patch b/patches.arch/x86-cpu-mtrr-support-top_mem2-and-get-mtrr-number.patch
new file mode 100644
index 0000000000..eda9ef26e6
--- /dev/null
+++ b/patches.arch/x86-cpu-mtrr-support-top_mem2-and-get-mtrr-number.patch
@@ -0,0 +1,55 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Sun, 23 Sep 2018 17:34:16 +0800
+Subject: x86/cpu/mtrr: Support TOP_MEM2 and get MTRR number
+Git-commit: 39dc6f154dac134e4612827cb5283934c1862cb8
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+The Hygon Dhyana CPU has a special MSR way to force WB for memory >4GB,
+and support TOP_MEM2. Therefore, it is necessary to add Hygon Dhyana
+support in amd_special_default_mtrr().
+
+The number of variable MTRRs for Hygon is 2 as AMD's.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Reviewed-by: Borislav Petkov <bp@suse.de>
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: x86@kernel.org
+Cc: thomas.lendacky@amd.com
+Link: https://lkml.kernel.org/r/8246f81648d014601de3812ade40e85d9c50d9b3.1537533369.git.puwen@hygon.cn
+---
+ arch/x86/kernel/cpu/mtrr/cleanup.c | 3 ++-
+ arch/x86/kernel/cpu/mtrr/main.c | 2 +-
+ 2 files changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/cleanup.c
+index 765afd599039..3668c5df90c6 100644
+--- a/arch/x86/kernel/cpu/mtrr/cleanup.c
++++ b/arch/x86/kernel/cpu/mtrr/cleanup.c
+@@ -831,7 +831,8 @@ int __init amd_special_default_mtrr(void)
+ {
+ u32 l, h;
+
+- if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
++ if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
++ boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
+ return 0;
+ if (boot_cpu_data.x86 < 0xf)
+ return 0;
+diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c
+index 9a19c800fe40..507039c20128 100644
+--- a/arch/x86/kernel/cpu/mtrr/main.c
++++ b/arch/x86/kernel/cpu/mtrr/main.c
+@@ -127,7 +127,7 @@ static void __init set_num_var_ranges(void)
+
+ if (use_intel())
+ rdmsr(MSR_MTRRcap, config, dummy);
+- else if (is_cpu(AMD))
++ else if (is_cpu(AMD) || is_cpu(HYGON))
+ config = 2;
+ else if (is_cpu(CYRIX) || is_cpu(CENTAUR))
+ config = 8;
+
diff --git a/series.conf b/series.conf
index 65c84a662b..1e174fb959 100644
--- a/series.conf
+++ b/series.conf
@@ -40255,6 +40255,7 @@
patches.arch/x86-corruption-check-fix-panic-in-memory_corruption_check-when-boot-option-without-value-is-provided
patches.arch/x86-cpu-create-hygon-dhyana-architecture-support-file.patch
patches.arch/x86-cpu-get-cache-info-and-setup-cache-cpumap-for-hygon-dhyana.patch
+ patches.arch/x86-cpu-mtrr-support-top_mem2-and-get-mtrr-number.patch
patches.fixes/0001-x86-xen-Fix-boot-loader-version-reported-for-PVH-gue.patch
patches.suse/msft-hv-1772-x86-hyperv-Suppress-PCI-Fatal-No-config-space-access.patch
patches.suse/msft-hv-1773-x86-hyperv-Remove-unused-include.patch