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authorPetr Tesarik <ptesarik@suse.cz>2019-08-20 15:23:24 +0200
committerPetr Tesarik <ptesarik@suse.cz>2019-08-20 15:23:24 +0200
commitb706dfc8718287e633650bfd55dfdae37b63c445 (patch)
tree54e61e464ef2dbcdaeac048d937fa9dd4ac9ecf8
parenta48976fb9166aafaf369b2954a6317a0735c2b38 (diff)
parent5872e42f68d898df9a1e0f09a8030e5ea353df8c (diff)
Merge branch 'users/tiwai/SLE15-SP1/for-next' into SLE15-SP1
Pull DRM fixes from Takashi Iwai
-rw-r--r--patches.drm/drm-amd-display-Remove-redundant-non-zero-and-overfl.patch50
-rw-r--r--patches.drm/drm-amd-display-num-of-sw-i2c-aux-engines-less-than-.patch258
-rw-r--r--patches.drm/drm-amdgpu-added-support-2nd-UVD-instance.patch63
-rw-r--r--patches.drm/drm-amdgpu-change-VEGA-booting-with-firmware-loaded-.patch58
-rw-r--r--series.conf4
5 files changed, 433 insertions, 0 deletions
diff --git a/patches.drm/drm-amd-display-Remove-redundant-non-zero-and-overfl.patch b/patches.drm/drm-amd-display-Remove-redundant-non-zero-and-overfl.patch
new file mode 100644
index 0000000000..225ce56264
--- /dev/null
+++ b/patches.drm/drm-amd-display-Remove-redundant-non-zero-and-overfl.patch
@@ -0,0 +1,50 @@
+From 56780940389a344a949d53ed7be77012a20ced7a Mon Sep 17 00:00:00 2001
+From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com>
+Date: Wed, 1 Aug 2018 10:20:53 -0400
+Subject: [PATCH] drm/amd/display: Remove redundant non-zero and overflow check
+Git-commit: 56780940389a344a949d53ed7be77012a20ced7a
+Patch-mainline: v4.20-rc1
+References: bsc#1145946
+
+[Why]
+Unsigned int is guaranteed to be >= 0, and read_channel_reply checks for
+overflows. read_channel_reply also returns -1 on error, which is what
+dc_link_aux_transfer is expected to return on error.
+
+[How]
+Remove the if-statement. Return result of read_channel_reply directly.
+
+Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
+Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 10 +++-------
+ 1 file changed, 3 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+index 8def0d9fa0ff..506a97e16956 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+@@ -666,13 +666,9 @@ int dc_link_aux_transfer(struct ddc_service *ddc,
+
+ switch (operation_result) {
+ case AUX_CHANNEL_OPERATION_SUCCEEDED:
+- res = returned_bytes;
+-
+- if (res <= size && res >= 0)
+- res = aux_engine->funcs->read_channel_reply(aux_engine, size,
+- buffer, reply,
+- &status);
+-
++ res = aux_engine->funcs->read_channel_reply(aux_engine, size,
++ buffer, reply,
++ &status);
+ break;
+ case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
+ res = 0;
+--
+2.16.4
+
diff --git a/patches.drm/drm-amd-display-num-of-sw-i2c-aux-engines-less-than-.patch b/patches.drm/drm-amd-display-num-of-sw-i2c-aux-engines-less-than-.patch
new file mode 100644
index 0000000000..ae3acf77fc
--- /dev/null
+++ b/patches.drm/drm-amd-display-num-of-sw-i2c-aux-engines-less-than-.patch
@@ -0,0 +1,258 @@
+From 0e8e4fbf8d8905071c045f2922de55adbe1a6abe Mon Sep 17 00:00:00 2001
+From: Hersen Wu <hersenxs.wu@amd.com>
+Date: Tue, 21 Aug 2018 09:35:47 -0400
+Subject: [PATCH] drm/amd/display: num of sw i2c/aux engines less than num of connectors
+Git-commit: 0e8e4fbf8d8905071c045f2922de55adbe1a6abe
+Patch-mainline: v4.20-rc1
+References: bsc#1145946
+
+[why]
+AMD Stoney reference board, there are only 2 pipes (not include
+underlay), and 3 connectors. resource creation, only
+2 I2C/AUX engines are created. Within dc_link_aux_transfer, when
+pin_data_en =2, refer to enengines[ddc_pin->pin_data->en] = NULL.
+NULL point is referred later causing system crash.
+
+[how]
+each asic design has fixed number of ddc engines at hw side.
+for each ddc engine, create its i2x/aux engine at sw side.
+
+Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 6 +++
+ drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 4 ++
+ drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 5 +++
+ drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 10 ++++--
+ drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 25 ++++++++++++++++
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 8 +++--
+ drivers/gpu/drm/amd/display/dc/inc/resource.h | 1
+ 7 files changed, 52 insertions(+), 7 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+@@ -371,7 +371,8 @@ static const struct resource_caps res_ca
+ .num_timing_generator = 6,
+ .num_audio = 6,
+ .num_stream_encoder = 6,
+- .num_pll = 3
++ .num_pll = 3,
++ .num_ddc = 6,
+ };
+
+ #define CTX ctx
+@@ -963,6 +964,9 @@ static bool construct(
+ "DC: failed to create output pixel processor!\n");
+ goto res_create_fail;
+ }
++ }
++
++ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ pool->base.engines[i] = dce100_aux_engine_create(ctx, i);
+ if (pool->base.engines[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+@@ -377,6 +377,7 @@ static const struct resource_caps carriz
+ .num_audio = 3,
+ .num_stream_encoder = 3,
+ .num_pll = 2,
++ .num_ddc = 3,
+ };
+
+ static const struct resource_caps stoney_resource_cap = {
+@@ -385,6 +386,7 @@ static const struct resource_caps stoney
+ .num_audio = 3,
+ .num_stream_encoder = 3,
+ .num_pll = 2,
++ .num_ddc = 3,
+ };
+
+ #define CTX ctx
+@@ -1295,7 +1297,9 @@ static bool construct(
+ "DC: failed to create output pixel processor!\n");
+ goto res_create_fail;
+ }
++ }
+
++ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ pool->base.engines[i] = dce110_aux_engine_create(ctx, i);
+ if (pool->base.engines[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+@@ -383,6 +383,7 @@ static const struct resource_caps polari
+ .num_audio = 6,
+ .num_stream_encoder = 6,
+ .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
++ .num_ddc = 6,
+ };
+
+ static const struct resource_caps polaris_11_resource_cap = {
+@@ -390,6 +391,7 @@ static const struct resource_caps polari
+ .num_audio = 5,
+ .num_stream_encoder = 5,
+ .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
++ .num_ddc = 5,
+ };
+
+ #define CTX ctx
+@@ -1245,6 +1247,9 @@ static bool construct(
+ "DC:failed to create output pixel processor!\n");
+ goto res_create_fail;
+ }
++ }
++
++ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ pool->base.engines[i] = dce112_aux_engine_create(ctx, i);
+ if (pool->base.engines[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+@@ -402,6 +402,7 @@ static const struct resource_caps res_ca
+ .num_audio = 7,
+ .num_stream_encoder = 6,
+ .num_pll = 6,
++ .num_ddc = 6,
+ };
+
+ static const struct dc_debug_options debug_defaults = {
+@@ -1020,6 +1021,12 @@ static bool construct(
+ dm_error(
+ "DC: failed to create output pixel processor!\n");
+ }
++
++ /* check next valid pipe */
++ j++;
++ }
++
++ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ pool->base.engines[i] = dce120_aux_engine_create(ctx, i);
+ if (pool->base.engines[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+@@ -1027,9 +1034,6 @@ static bool construct(
+ "DC:failed to create aux engine!!\n");
+ goto res_create_fail;
+ }
+-
+- /* check next valid pipe */
+- j++;
+ }
+
+ /* valid pipe num */
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+@@ -366,6 +366,7 @@ static const struct resource_caps res_ca
+ .num_audio = 6,
+ .num_stream_encoder = 6,
+ .num_pll = 3,
++ .num_ddc = 6,
+ };
+
+ static const struct resource_caps res_cap_81 = {
+@@ -373,6 +374,7 @@ static const struct resource_caps res_ca
+ .num_audio = 7,
+ .num_stream_encoder = 7,
+ .num_pll = 3,
++ .num_ddc = 6,
+ };
+
+ static const struct resource_caps res_cap_83 = {
+@@ -380,6 +382,7 @@ static const struct resource_caps res_ca
+ .num_audio = 6,
+ .num_stream_encoder = 6,
+ .num_pll = 2,
++ .num_ddc = 2,
+ };
+
+ static const struct dce_dmcu_registers dmcu_regs = {
+@@ -935,7 +938,9 @@ static bool dce80_construct(
+ dm_error("DC: failed to create output pixel processor!\n");
+ goto res_create_fail;
+ }
++ }
+
++ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
+ if (pool->base.engines[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+@@ -1131,6 +1136,16 @@ static bool dce81_construct(
+ }
+ }
+
++ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
++ pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
++ if (pool->base.engines[i] == NULL) {
++ BREAK_TO_DEBUGGER();
++ dm_error(
++ "DC:failed to create aux engine!!\n");
++ goto res_create_fail;
++ }
++ }
++
+ dc->caps.max_planes = pool->base.pipe_count;
+ dc->caps.disable_dp_clk_share = true;
+
+@@ -1312,6 +1327,16 @@ static bool dce83_construct(
+ goto res_create_fail;
+ }
+ }
++
++ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
++ pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
++ if (pool->base.engines[i] == NULL) {
++ BREAK_TO_DEBUGGER();
++ dm_error(
++ "DC:failed to create aux engine!!\n");
++ goto res_create_fail;
++ }
++ }
+
+ dc->caps.max_planes = pool->base.pipe_count;
+ dc->caps.disable_dp_clk_share = true;
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+@@ -500,6 +500,7 @@ static const struct resource_caps res_ca
+ .num_audio = 4,
+ .num_stream_encoder = 4,
+ .num_pll = 4,
++ .num_ddc = 4,
+ };
+
+ static const struct dc_debug_options debug_defaults_drv = {
+@@ -1292,7 +1293,11 @@ static bool construct(
+ dm_error("DC: failed to create tg!\n");
+ goto fail;
+ }
++ /* check next valid pipe */
++ j++;
++ }
+
++ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ pool->base.engines[i] = dcn10_aux_engine_create(ctx, i);
+ if (pool->base.engines[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+@@ -1300,9 +1305,6 @@ static bool construct(
+ "DC:failed to create aux engine!!\n");
+ goto fail;
+ }
+-
+- /* check next valid pipe */
+- j++;
+ }
+
+ /* valid pipe num */
+--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
+@@ -44,6 +44,7 @@ struct resource_caps {
+ int num_stream_encoder;
+ int num_pll;
+ int num_dwb;
++ int num_ddc;
+ };
+
+ struct resource_straps {
diff --git a/patches.drm/drm-amdgpu-added-support-2nd-UVD-instance.patch b/patches.drm/drm-amdgpu-added-support-2nd-UVD-instance.patch
new file mode 100644
index 0000000000..bafc60356e
--- /dev/null
+++ b/patches.drm/drm-amdgpu-added-support-2nd-UVD-instance.patch
@@ -0,0 +1,63 @@
+From d4e838431d56ac132a7f387b34e5c9f227dce428 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 14 Aug 2018 14:53:52 -0400
+Subject: [PATCH] drm/amdgpu: added support 2nd UVD instance
+Git-commit: d4e838431d56ac132a7f387b34e5c9f227dce428
+Patch-mainline: v4.20-rc1
+References: bsc#1143331
+
+[ backport note: the code change for psp_v11_0.c is dropped -- tiwai ]
+
+Added psp fw loading support for vega20 2nd UVD instance.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 1 +
+ drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 3 ++-
+ drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 7 +++++++
+ 3 files changed, 10 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+@@ -193,6 +193,7 @@ enum AMDGPU_UCODE_ID {
+ AMDGPU_UCODE_ID_STORAGE,
+ AMDGPU_UCODE_ID_SMC,
+ AMDGPU_UCODE_ID_UVD,
++ AMDGPU_UCODE_ID_UVD1,
+ AMDGPU_UCODE_ID_VCE,
+ AMDGPU_UCODE_ID_VCN,
+ AMDGPU_UCODE_ID_MAXIMUM,
+--- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
++++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
+@@ -189,7 +189,8 @@ enum psp_gfx_fw_type
+ GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM = 20,
+ GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM = 21,
+ GFX_FW_TYPE_RLC_RESTORE_LIST_CNTL = 22,
+- GFX_FW_TYPE_MAX = 23
++ GFX_FW_TYPE_UVD1 = 23,
++ GFX_FW_TYPE_MAX = 24
+ };
+
+ /* Command to load HW IP FW. */
+--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+@@ -441,6 +441,13 @@ static int uvd_v7_0_sw_init(void *handle
+ adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw;
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
++
++ if (adev->uvd.num_uvd_inst == UVD7_MAX_HW_INSTANCES_VEGA20) {
++ adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].ucode_id = AMDGPU_UCODE_ID_UVD1;
++ adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].fw = adev->uvd.fw;
++ adev->firmware.fw_size +=
++ ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
++ }
+ DRM_INFO("PSP loading UVD firmware\n");
+ }
+
diff --git a/patches.drm/drm-amdgpu-change-VEGA-booting-with-firmware-loaded-.patch b/patches.drm/drm-amdgpu-change-VEGA-booting-with-firmware-loaded-.patch
new file mode 100644
index 0000000000..b0cac8f480
--- /dev/null
+++ b/patches.drm/drm-amdgpu-change-VEGA-booting-with-firmware-loaded-.patch
@@ -0,0 +1,58 @@
+From bfcea5204287b0a09dac71fa56a5d066d94d9bb1 Mon Sep 17 00:00:00 2001
+From: Feifei Xu <Feifei.Xu@amd.com>
+Date: Tue, 14 Aug 2018 14:53:53 -0400
+Subject: [PATCH] drm/amdgpu:change VEGA booting with firmware loaded by PSP
+Git-commit: bfcea5204287b0a09dac71fa56a5d066d94d9bb1
+Patch-mainline: v4.20-rc1
+References: bsc#1143331
+
+With PSP firmware loading, TMR mc address is supposed to be used.
+
+Signed-off-by: James Zhu <James.Zhu@amd.com>
+Acked-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 13 +++++++++----
+ 1 file changed, 9 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+index 79cb3787a282..a289f6a20b6b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+@@ -671,9 +671,14 @@ static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
+ continue;
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+ WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
+- lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
++ i == 0 ?
++ adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo:
++ adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_lo);
+ WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
+- upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
++ i == 0 ?
++ adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi:
++ adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_hi);
++ WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
+ offset = 0;
+ } else {
+ WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
+@@ -681,10 +686,10 @@ static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
+ WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
+ upper_32_bits(adev->uvd.inst[i].gpu_addr));
+ offset = size;
++ WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,
++ AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
+ }
+
+- WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,
+- AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
+ WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size);
+
+ WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
+--
+2.16.4
+
diff --git a/series.conf b/series.conf
index 64f0def2d8..f6b9504939 100644
--- a/series.conf
+++ b/series.conf
@@ -42249,9 +42249,13 @@
patches.drm/drm-i915-Attach-the-pci-match-data-to-the-device-upo.patch
patches.drm/drm-i915-Move-final-cleanup-of-drm_i915_private-to-i.patch
patches.drm/0001-drm-rcar-du-Update-Gen3-output-limitations.patch
+ patches.drm/drm-amd-display-Remove-redundant-non-zero-and-overfl.patch
patches.drm/0037-drm-amdgpu-fix-integer-overflow-test-in-amdgpu_bo_li.patch
+ patches.drm/drm-amdgpu-added-support-2nd-UVD-instance.patch
+ patches.drm/drm-amdgpu-change-VEGA-booting-with-firmware-loaded-.patch
patches.drm/drm-amdgpu-add-missing-CHIP_HAINAN-in-amdgpu_ucode_g.patch
patches.drm/0005-drm-amdgpu-Revert-kmap-PDs-PTs-in-amdgpu_vm_update_d.patch
+ patches.drm/drm-amd-display-num-of-sw-i2c-aux-engines-less-than-.patch
patches.drm/0001-drm-amdgpu-Fix-SDMA-TO-after-GPU-reset-v3.patch
patches.drm/0001-drm-hisilicon-hibmc-Do-not-carry-error-code-in-HiBMC.patch
patches.drm/0001-drm-hisilicon-hibmc-Don-t-overwrite-fb-helper-surfac.patch